1. Field of the Invention
The present invention generally relates to a circuit layout structure. In particular, the present invention relates to a special circuit layout structure. In this circuit layout structure, a metal interconnect which is surrounded by a metal interlayer dielectric layer and a metal pattern within a scrub line are suitably segregated to reduce an adverse capacitance charging effect.
2. Description of the Prior Art
In the semiconductor manufacturing processes, an etching step is usually employed to construct a pre-determined pattern in a pre-determined material layer. FIGS. 1-3 illustrate a process to construct a pre-determined pattern in a pre-determined material layer by a conventional etching step in the prior art. First, please refer to FIG. 1, a wafer 100 is provided. There are multiple material layers which have been constructed on the wafer 100. For example, an interlayer dielectric layer 110 is disposed on the silicon substrate 101, and a metal contact plug 111 is in the interlayer dielectric layer 110 and surrounded by the interlayer dielectric layer 110. A metal interlayer dielectric layer 120 is disposed on the metal contact plug 111 and covers the interlayer dielectric layer 110. An etching mask 130 is formed on the metal interlayer dielectric layer 120 and has a pre-determined pattern 131. The etching mask 130 may be a conductive mask of composite layers such as silicon oxynitride, conductive titanium nitride, tetraethoxysilane (TEOS) and/or a low-k material . . . etc.
Then, as shown in FIG. 2, a suitable etchant under a plasma circumstance is used to etch the underlying metal interlayer dielectric layer 120 to transfer the pre-determined pattern 131 into the metal interlayer dielectric layer 120 to form a trench 121 for defining metal wires and to expose the metal contact plug 111 in the interlayer dielectric layer 110, as shown in FIG. 2. The trench 121 which is formed by such etch step is useful in forming the electrical connection to the metal contact plug 111.
However, not all of the trenches 121 may successfully expose the metal contact plug 111 in the interlayer dielectric layer 110 as expected, as shown in FIG. 3. Sometimes, some charged etching residues 113, for example some polymers, cannot leave the trench 121 along with the suitable etchant under the plasma circumstance, hence too many etching residues 113 block the bottom of the trench 121 so that the metal contact plug 111 in the interlayer dielectric layer 110 cannot be exposed. This result is called an “opening failure.”
One reason of the accumulation of the etching residues 113 is that, during the etching step, an ESD device (not shown) is often used to fix the wafer 100. Due to the static charge generated by the ESD device, an adverse capacitance through the induction of the substrate 101 may be formed between the conductive metal mask 130, such as a TiN mask, and the metal pattern 114 in the scrub line 103. As a result, this attracts more charged etching residues 113 to accumulate in the trench 121 in the chip region 102 and keeps the underlying metal contact plug 111 from being exposed. No effective electrical connection thus can be formed.
Accordingly, a novel circuit layout structure is still needed to improve the yield of the etching step, in particular to avoid too many etching residues blocking the trenches and failing to expose the underlying metal contact plugs when a metal interconnect is adjacent to a scrub line with a metal pattern.